In many serial communications systems, there is often a need to determine whether a valid input signal is present. Typically, this can be accomplished by first detecting the amplitude of an incoming signal. If the amplitude is less than a predetermined value, the signal may be considered invalid. On the other hand, if the amplitude is greater than the predetermined value, the signal may be considered valid. The rationale behind this general approach is to substantially eliminate the possibility of random noise appearing like a signal when there may actually be no usable signal present. A squelch detector is typically used in serial communications to suppress (e.g., via a logic level squelch indication) an input if that input is detected to be below or within the predetermined value or threshold. Accordingly, an input signal may not be considered “valid” and may instead be considered “squelch” or invalid until that signal is outside a predetermined invalid range or greater than the threshold.
Referring now to FIG. 1, a schematic diagram showing a conventional squelch detector circuit (see, e.g., U.S. Patent Application Publication No. 2003/0112058) is indicated by the general reference character 100. This approach includes hysteretic comparator 102, followed by edge detector 104, peak detector 110, and another hysteretic comparator 112. Comparator 102 may take differential signal RX+/RX−, provide a gain of the differential signal by a fixed amount, and then convert the differential signal to a single-ended signal. Edge detector 104, including delay/inverter 106 and AND gate 108, may only trip if its threshold is exceeded (e.g., the signal from comparator 102 is sufficiently long). If the signal from comparator 102 is sufficiently long, edge detector 104 may output a pulse of fixed duration (e.g., based on the amount of delay in delay/inverter 106). Peak detector 110, including diode D1, resistor R1, and capacitor C1, may then sample the signal from edge detector 104 and hold the latest value for an amount of time, as determined by the RC time constant of peak detector 110. As long as another signal edge or transition is detected by edge detector 104 prior to the decay of the signal at the output of peak detector 110, this voltage can be sustained and a continuously valid squelch signal may result. Comparator 112 can then convert the output of peak detector 110 into a logic level (e.g., “0” or “1”) by comparing this peak detected value to a fixed reference (not shown).
One drawback of conventional approaches, such as that shown in FIG. 1, is the overall complexity of the architecture. What is needed is a reliable and simplified approach for squelch detection suitable for serial communication applications.